Systems and methods for timing recovery in near-field communication

ABSTRACT

A method for inductively-coupled communications is described. The method includes receiving a signal. The method also includes analyzing the signal to estimate a symbol timing error. Estimating the symbol timing error may include comparing a location of a pause, a low-to-high or a high-to-low transition in the received signal with an ideal location of a pause or a transition. The method further includes adjusting symbol timing to correct for the symbol timing error.

RELATED APPLICATIONS

This application is related to and claims priority from U.S. ProvisionalPatent Application Ser. No. 61/949,829, filed Mar. 7, 2014, for “TimeTracking Loop for Target Receiver of Near-Field Communication.”

TECHNICAL FIELD

The described technology generally relates to an apparatus and method ofwireless communication. More particularly, the technology relates to areceiver design and optimization for wireless near-field communication(NFC).

BACKGROUND

The wireless communication environment in a home or an office generallyincludes a number of independently developed radio access technologiesand standards. These technologies were initially designed for targetapplications and they perform relatively well for these applications. Ina typical home or office environment, an access to content (e.g., web,video, etc.) is provided to a broadband modem through the home-owner'sIP backhaul connection. For instance, mobile services are providedthrough the cellular network, through either a macro cell or a femtocell located within the home or office. Wireless local area network(WLAN) access points (APs) provide data connectivity between computers,cell phones, laptops, printers, and other wireless stations using802.11-based Wi-Fi technology.

Another communication medium currently being implemented in electronicequipment is near-field communication (NFC). The use of NFC interfacesin electronic equipment provides portable devices with functions similarto those of non-contact integrated circuit cards (e.g., radio frequencyidentification (RFID) cards). In addition, electronic equipment providedwith NFC interfaces is typically capable of operating as radio frequency(RF) readers and/or writers to communicate with other NFC devices. Abasic aspect of NFC is the use of electromagnetic waves in an RF rangeand the transmission of information contents is realized over a shortdistance only, for instance in a range of about several centimeters.

RFID technology is widely used in many areas such as publictransportation services, object tracking systems and home management,and it is growing rapidly. It can handle the information from tags. TheRFID application technology is currently integrated in one chip. 13.56MHz RFID reader specification is based on the standard including ISO14443 type-A, type-B, ISO 15693 and ISO 18000-3 standards. In NFC or anRFID application, a transmitter of a proximity coupling device (PCD),also known as a reader, writer or initiator, may use one of followingthree linear codes, followed by an amplitude modulation: (1) amodified-Miller code used for NFC type-A, (2) a non-return-to-zero (NRZ)code used in NFC type-B, and (3) a Manchester code used in NFC type-F.

SUMMARY

A method for inductively-coupled communications is described. The methodincludes receiving a signal. The method also includes analyzing thesignal to estimate a symbol timing error. The method further includesadjusting symbol timing to correct for the symbol timing error.

Estimating the symbol timing error may include comparing a location of apause, a low-to-high or a high-to-low transition in the received signalwith an ideal location of a pause or a transition. Estimating the symboltiming error may include detecting timing of a beginning of eachcharacter. Estimating the symbol timing error may be based on the outputof one or more accumulators that accumulate samples during differentperiods in a bit duration.

Adjusting the symbol timing may include incrementing initial symboltiming by a fixed bit duration.

Modulation may be performed in accordance with a near-fieldcommunication (NFC) type-A standard. In this case, estimating the symboltiming error may include comparing a location of a pause in the receivedsignal with an ideal location of a pause corresponding to a decoded bit.Adjusting the symbol timing may include adding or subtracting theestimated symbol timing error from a sample counter.

Modulation may be performed in accordance with an NFC communicationtype-F standard. In this case, estimating the symbol timing error mayinclude comparing a location of a low-to-high or a high-to-lowtransition in the received signal with an ideal location of atransition. Adjusting the symbol timing may include adding orsubtracting the estimated symbol timing error from a sample counter.

Modulation may be performed in accordance with an NFC type-B standard inwhich data is sent in characters. In this case, estimating the symboltiming error may include detecting timing of a beginning of eachcharacter. Adjusting the symbol timing may include incrementing initialsymbol timing by a fixed bit duration.

In another configuration in which modulation may be performed inaccordance with an NFC type-B standard in which data is sent incharacters, estimating the symbol timing error may include detectingtiming of a beginning of each character and comparing a location of alow-to-high or high-to-low transition in the received signal with anideal location of a transition. Adjusting the symbol timing may includeadding or subtracting the estimated symbol timing error from a samplecounter.

A receiver for inductively-coupled communications is also described. Thereceiver includes a slicer that receives output samples from ananalog-to-digital converter (ADC) and generates a bit stream. Thereceiver also includes an acquisition block that acquires packets andinitial symbol timing. The receiver further includes a decoder. Thereceiver additionally includes a time tracker block that analyzes thesignal to estimate a symbol timing error based on the initial symboltiming and the bit stream. The time tracker block also adjusts symboltiming to correct for the symbol timing error. The time tracker blockprovides the symbol timing to the decoder.

Estimating the symbol timing error may include the time tracker blockcomparing a location of a pause, a low-to-high or a high-to-lowtransition in the received signal with an ideal location of a pause or atransition. The time tracker block may estimate the symbol timing errorbased on the output of one or more accumulators that accumulate samplesduring different periods in a bit duration.

When modulation is performed in accordance with an NFC type-A standard,the time tracker block may estimate the symbol timing error by comparinga location of a pause in a received signal with an ideal location of apause corresponding to a decoded bit. The time tracker block may adjustthe symbol timing by adding or subtracting the estimated symbol timingerror from a sample counter.

When modulation is performed in accordance with an NFC type-F standard,the time tracker block may estimate the symbol timing error by comparinga location of a low-to-high or a high-to-low transition in a receivedsignal with an ideal location of a transition. The time tracker blockmay adjust the symbol timing by adding or subtracting the estimatedsymbol timing error from a sample counter.

When modulation is performed in accordance with an NFC type-B standardin which data is sent in characters, the time tracker block may estimatethe symbol timing error by detecting timing of the beginning of eachcharacter. The time tracker block may adjust the symbol timing byincrementing initial symbol timing by a fixed bit duration.

In another configuration, when modulation is performed in accordancewith an NFC type-B standard in which data is sent in characters, thetime tracker block may estimate the symbol timing error by detectingtiming of a beginning of each character and comparing a location of alow-to-high or high-to-low transition in a received signal with an ideallocation of a transition. The time tracker block may adjust the symboltiming by adding or subtracting the estimated symbol timing error from asample counter.

An apparatus for inductively-coupled communications is also described.The apparatus includes means for receiving a signal. The apparatus alsoincludes means for analyzing the signal to estimate a symbol timingerror. The apparatus further includes means for adjusting symbol timingto correct for the symbol timing error.

A computer-program product for inductively-coupled communications isalso described. The computer-program product includes a non-transitorycomputer-readable medium having instructions thereon. The instructionsinclude code for causing an electronic device to receive a signal. Theinstructions also include code for causing the electronic device toanalyze the signal to estimate a symbol timing error. The instructionsfurther include code for causing the electronic device to adjust symboltiming to correct for the symbol timing error.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating one configuration of a near-fieldwireless communication system for timing recovery;

FIG. 2 is a flow diagram illustrating a method for timing recovery inNFC;

FIG. 3 is a block diagram illustrating an NFC system;

FIG. 4 is a block diagram illustrating an exemplary schematic of an NFCsystem including a transceiver and a remote unit;

FIG. 5 illustrates an exemplary diagram of a modified-Miller codepattern, an NRZ (non-return-to-zero) code pattern and a Manchester codepattern;

FIG. 6 illustrates examples of signal waveforms that are processedinside the NFC receiver of FIG. 1;

FIG. 7 is a block diagram illustrating symbol timing for NFC type-A;

FIG. 8 illustrates the adjustment timing and the behavior of a samplecounter for the faster clock case for NFC type-A;

FIG. 9 illustrates the adjustment timing and the behavior of a samplecounter for the slower clock case for NFC type-A;

FIG. 10 is a block diagram illustrating a configuration of a timetracker block when modulation is performed in accordance with NFCtype-A;

FIG. 11 is a flow diagram illustrating one possible method forestimating symbol timing error where modulation is performed inaccordance with NFC type-A;

FIG. 12 is a block diagram illustrating symbol timing for NFC type-F;

FIG. 13 illustrates the behavior of the sample counter and symbol timingin the faster clock case for NFC type-F;

FIG. 14 illustrates the behavior of the sample counter and symbol timingin the slower clock case for NFC type-F;

FIG. 15 is a block diagram illustrating a configuration of a timetracker block when modulation is performed in accordance with NFCtype-F;

FIG. 16 is a flow diagram illustrating one possible method forestimating symbol timing error where modulation is performed inaccordance with NFC type-F;

FIG. 17 is a flow diagram illustrating one possible method forestimating symbol timing error where modulation is performed inaccordance with NFC type-B;

FIG. 18 is a flow diagram illustrating another possible method forestimating symbol timing error where modulation is performed inaccordance with NFC type-B; and

FIG. 19 illustrates certain components that may be included within anelectronic device.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appendeddrawings is intended as a description of exemplary implementations ofthe disclosure and is not intended to represent the only implementationsin which the disclosure may be practiced. The term “exemplary” usedthroughout this description means “serving as an example, instance, orillustration,” and should not necessarily be construed as preferred oradvantageous over other exemplary implementations. The detaileddescription includes specific details for the purpose of providing athorough understanding of the exemplary implementations of thedisclosure. In some instances, some devices are shown in block diagramform.

While for purposes of simplicity of explanation, the methodologies areshown and described as a series of acts, it is to be understood andappreciated that the methodologies are not limited by the order of acts,as some acts may, in accordance with one or more aspects, occur indifferent orders and/or concurrently with other acts from that shown anddescribed herein. For example, those skilled in the art will understandand appreciate that a methodology could alternatively be represented asa series of interrelated states or events, such as in a state diagram.Moreover, not all illustrated acts may be required to implement amethodology in accordance with one or more aspects.

Various configurations are now described with reference to the Figures,where like reference numbers may indicate functionally similar elements.The systems and methods as generally described and illustrated in theFigures herein could be arranged and designed in a wide variety ofdifferent configurations. Thus, the following more detailed descriptionof several configurations, as represented in the Figures, is notintended to limit scope, as claimed, but is merely representative of thesystems and methods.

FIG. 1 is a block diagram illustrating one configuration of a near-fieldwireless communication system 100 for timing recovery. The wirelesscommunication system 100 may include an initiator near-fieldcommunication (NFC) device 102 and a target NFC device 104. Aspects ofthe present disclosure relate to the initiator NFC device 102transmitting a signal 118 (e.g., packet) and target NFC device 104receiving the signal 118.

NFC is an inductively coupled communication. Therefore, the initiatorNFC device 102 may also be referred to as an inductively coupledcommunication device. The antenna 116 of the initiator NFC device 102produces a radiated field (also referred to as a magnetic field or anelectromagnetic field) that is received by the antenna 122 of the targetNFC device 104. In the context of near-field communications, there aretwo devices communicating: an initiator and a target. The initiator NFCdevice 102 has a transmitter 106 and a receiver (for the sake ofclarity, the initiator receiver is not shown in FIG. 1). The target alsohas a transmitter and a receiver 120 (for the sake of clarity, thetarget transmitter is not shown in FIG. 1). The initiator NFC device 102may also be referred to as a poller, polling device or initiator. Thetarget NFC device 104 may also be referred to as a listener, listeningdevice or target.

The initiator NFC device 102 and the target NFC device 104 may use oneor more NFC signaling technologies to communicate with each other. TheNFC signaling technologies may include NFC type-A, NFC type-B and NFCtype-F. The NFC signaling technologies differ in the modulation schemesemployed.

NFC has four different tag types, which support a subset of the NFCsignaling technologies. Type 1 tags (T1T) use NFC type-A communicationwithout data collision protection. Type 2 tags (T2T) use NFC type-Bcommunication with anti-collision. Type 3 tags (T3T) use NFC type-F withanti-collision. Type 4 tags (T4T) can use either NFC type-A (T4AT) orNFC type-B (T4BT) with anti-collision.

In one configuration, the initiator NFC device 102 and the target NFCdevice 104 may be operable to communicate using NFC through variousinterfaces, such as a frame radio frequency (RF) interface, ISO-dataexchange protocol (DEP) RF interface and NFC-DEP RF interface. Inanother configuration, the initiator NFC device 102 and the target NFCdevice 104 may establish an NFC-DEP RF protocol-based communication linkwith link layer connections defined through a logical link controlprotocol (LLCP). In still another configuration, the initiator NFCdevice 102 and the target NFC device 104 may be operable to be connectedto an access network and/or core network (e.g., a CDMA network, a GPRSnetwork, a UMTS network, and other types of wireline and wirelesscommunication networks).

The initiator NFC device 102 may poll for nearby NFC devices. The targetNFC device 104 may begin to listen when it comes within a fewcentimeters of the initiator NFC device 102. The initiator NFC device102 will then communicate with the target NFC device 104 in order todetermine which signaling technologies can be used. In one case, theinitiator NFC device 102 may be acting as a reader. In one example, auser may place a target NFC device 104 in the vicinity of the initiatorNFC device 102 to initiate a payment transaction.

The initiator NFC device 102 may generate an RF field to communicatewith the target NFC device 104. The initiator NFC device 102 maymodulate the RF field to send a signal (e.g., data) to the target NFCdevice 104. Once the target NFC device 104 receives that signal, theinitiator NFC device 102 may transmit a continuous wave to maintain theRF field. The continuous wave may have a carrier frequency. In the caseof NFC, the carrier frequency may be 13.56 megahertz (MHz).

The target NFC device 104 may receive the RF field. The target NFCdevice 104 may respond by performing modulation on top of the continuouswave. The initiator NFC device 102 may receive the modulated signal andmay try to decode it.

The target NFC device 104 may receive a signal 118 from the initiatorNFC device 102. The signal 118 may be sent on a channel. The signal 118may include data that is sent in one or more packets.

On the initiator NFC device 102 side, an information source 108generates information bits (0, 1) and sends the information bits to aline coder 110. The line coder 110 may code the information bits. Theline coder 110 may generate corresponding coded bits using an encodingmechanism. Examples of the coding mechanism include a non-return-to-zero(NRZ) coding mechanism, a Manchester coding mechanism and amodified-Miller coding mechanism.

The coded bits are then sent into a pulse shaping filter (PSF) 112. ThePSF 112 generates a signal pulse or symbol for one or multiple codedbits. The modulator 114 modulates the signal symbols generated by thePSF 112. The transmit antenna 116 transmits the modulated signal symbolsto the receiver 120 through the channel. The transmit antenna 116 mayinclude a coil.

In one configuration, the receiver 120 of the target NFC device 104includes a receive antenna 122, an envelope detector 124, a low passfilter (LPF) 126, an ADC 128, a slicer 130, an acquisition block 132, atime tracker block 134, the decoder 136 and an information bit sink 138.Certain elements/blocks may be removed from or additionalelements/blocks may be added to the system 100 illustrated in FIG. 1.Furthermore, two or more elements/blocks may be combined into a singleelement/block, or a single element/block may be realized as multipleelements/blocks. For example, the antenna 122, the envelope detector124, the LPF 126 and ADC 128 may be realized as a single element such asthe receiver interface 140. Furthermore, one or both of the slicer 130and the acquisition block 132 may be incorporated into the decoder 136.

The receive antenna 122 receives the modulated symbols sent by theinitiator NFC device 102 through the channel. The receive antenna 122may include a coil. In one configuration, the envelope detector 124 isdisposed in an initial position in the receiver 120 signal processingflow. The envelope detector 124 may carry out demodulation of themodulated symbols received by the receiver antenna 122 and generatedemodulated symbols.

The demodulated symbols are sent into the LPF 126. The LPF 126 mayreduce carrier signal ripples and high frequency noise from thedemodulated symbols. The carrier signal ripples may be made by a carrierwhich carries the modulated symbols and may cause bit errors on thedecoder 136.

The demodulated symbols filtered by the LPF 126 are sent into the ADC128. In one configuration, the ADC 128 is a multi-bit ADC and generatesmulti-bit output samples. In another configuration, the ADC 128 is a1-bit ADC and generates 1-bit output per sample.

The output samples generated by the ADC 128 are sent into the slicer130. The slicer 130 may also be referred to as an adaptive slicer or aquantizer. In one configuration, the slicer 130 includes a digitalmultiplexer. The slicer 130 generates a bit stream. The slicer 130 mayconvert the input sequence of M-bit samples into the output sequence ofN-bit samples and remove a time-varying DC component from the inputsequence. In one configuration, M and N are positive integer numbers,and M is greater than N. For example, M may be 3 or greater, and N maybe 2 or 1.

In one configuration, the slicer 130 may convert an input sequence of atleast 3-bit samples into an output sequence of 1-bit samples. The slicer130 maps the output sequence of multi-bit samples into binary symbols.In another configuration, the slicer 130 may convert an input sequenceof at least 3-bit samples into an output sequence of 2-bit samples.

The bit stream from the slicer 130 is sent into the acquisition block132, the time tracker block 134 and the decoder 136. The acquisitionblock 132 acquires packets and initial symbol timing 146 (i.e., bitboundary information) from the bit stream. The bit boundary may belocated between neighboring quarters of a bit stream (e.g., the lastquarter of an information bit and the first quarter of the subsequentinformation bit) for the modified Miller code, and between neighboringhalves of a bit stream for the Manchester code.

When a packet is acquired, the decoder 136 may be activated. The decoder136 decodes information bits from the output from the slicer 130 andsends the decoded information bits to the sink 138. Since theacquisition block 132 and the decoder block 136 operate on binarysymbols or symbols whose bit-width is at most two, they can beimplemented with low hardware complexity, compared with the blocksoperating on multi-bit ADC outputs (e.g., a 3-bit ADC or higherresolution ADCs).

In a typical implementation, the receiver 120 of the target NFC device104 derives its clock using a phase-locked loop (PLL) based on thecarrier generated by the transmitter 106 of the initiator NFC device102. If the derived clock is accurate, the receiver clock and thetransmitter clock are synchronized. Hence, the receiver 120 candetermine bit boundaries (i.e., symbol timing 148) simply using a samplecounter 142.

In reality, however, the derived clock may be inaccurate. For example,the PLL may suffer a cycle slip, especially if the modulated carrier hasvery low amplitude (as NFC uses amplitude modulation). Because the NFCtype-A standard uses a modulation index of 90% to 100% for the 106 kbpsmode, the cycle slip can happen easily. The cycle slip may lead toerroneous bit boundaries and erroneous decoding of packet data.

In one configuration, a 27.12 MHz digital clock for a modem of thetarget NFC device 104 may be derived from the carrier generated by aninitiator using a phase locked loop (PLL) in a radio frequency analog(RFA) subsystem. It was observed that the digital clock frequency may beslightly higher (i.e., faster) than the ideal 27.12 MHz for a briefperiod depending on signal 118 strength, presence of overshoot in thereceive antenna 122 output signal, coupling and distance between theinitiator NFC device 102 and the target NFC device 104, etc. For longpackets, the accumulated clock drift may become significantly largerelative to the bit duration and lead to erroneous decoding.

In accordance with the present disclosure, a time tracking block(represented by the time tracker block 134 in FIG. 1) may be added to areceiver 120. In one implementation, the time tracker block 134 may beadded to a digital modem. The time tracker block 134 may compute andprovide symbol timing 148 to the decoder 136 based on the initial symboltiming 146 and the bit stream generated by the ADC 128 or the slicer130. In one configuration, the symbol timing 148 is a series of bitboundaries.

The time tracker block 134 adjusts bit boundaries based on the outputsignal of the ADC 128 or the slicer 130. This relaxes requirements onthe clock generation PLL (i.e., the clock generation PLL is allowed tointroduce cycle slips). Benefits may be realized by the time trackerblock 134 that tracks clock drift and adjusts bit boundaries used by thetarget decoder 136. There may be several advantages with such anapproach. First, the time tracker block 134 may ensure that packets aredecoded correctly, even for long packets, for which accumulated cycleslips may become huge. Second, analog circuits may be designed with lesscomponent cost. Third, analog circuits can be tuned (optimized forenergy harvesting, for example) without worrying about cycle slips.

In accordance with the present disclosure, the time tracker block 134can estimate bit boundary errors based on the output of the ADC 128 orthe slicer 130, and adjust bit boundaries. The time tracker block 134may analyze the signal 118 to estimate a symbol timing error 144. Thetime tracker block 134 may then adjust symbol timing 148 to correct forthe symbol timing error 144.

In one configuration, the time tracker block 134 may estimate the symboltiming error 144 by comparing a location of a low-to-high or ahigh-to-low transition in the received signal 118 with an ideal locationof a transition. For example, based on the initial symbol timing 146from the acquisition block 132, the time tracker block 134 may determinethe ideal location of a transition.

The time tracker block 134 may accumulate samples during differentperiods of a bit duration. For example, the time tracker block 134 mayobtain samples of the bit stream output of the slicer 130. By comparingthe samples to the ideal location of a transition, the time trackerblock 134 may determine the symbol timing error 144.

The time tracker block 134 may adjust the symbol timing 148 byincrementing the initial symbol timing 146. In one configuration, thetime tracker block 134 may adjust the symbol timing 148 by adding orsubtracting the estimated symbol timing error 144 from a sample counter142. In this configuration, the sample counter 142 may count the samplesfrom the start of symbol (as indicated by the initial symbol timing 146,for instance). In another configuration, the time tracker block 134 mayadjust the symbol timing 148 by incrementing initial symbol timing 146by a fixed bit duration.

The time tracker block 134 may estimate the symbol timing error 144 andadjust the symbol timing 148 based on the NFC modulation types. Asmentioned, there are three major modulation types in the NFC standards:type-A, type-B and type-F.

Type-A uses the modified-Miller code as a line code (i.e., basebandcode). The code has a low-level period in (1) the first quarter of a bitduration, (2) the third quarter of a bit duration, or (3) none of a bitduration. By estimating the location of the low-level period for the (1)and (2) cases relative to the start of a bit duration, it may bepossible to estimate the bit boundary error for the current bit andadjust the bit boundary of the following bit accordingly.

The basic idea of time tracking for NFC type-A is to monitor thelocation of a pause relative to the ideal location in a bit duration.Type-A uses three waveforms: bit 0A, bit 0B and bit 1. Bit 0A bears noinformation about clock drift because the waveform is a constanthigh-level. On the other hand, bit 0B has a pause during the firstquarter (abbreviated to Q1), and bit 1 during the third quarter(abbreviated to Q3).

For NFC type-A, the time tracker block 134 may estimate the symboltiming error 144 by comparing a location of a pause in the receivedsignal 118 with an ideal location of a pause corresponding to a decodedbit. The decoded bit may be received from the decoder 136 or may bedecoded by the time tracker block 134 itself. The time tracker block 134may adjust the symbol timing 148 by adding or subtracting the estimatedsymbol timing error 144 from the sample counter 142.

Type-B sends data in a chunk of 8 bits, called characters. Charactersare separated by a random amount of time, which is called extra guardtime in the standards. Hence, each character should be acquiredseparately. This implies that cycle slips can be accumulated only for8-bit durations. For NFC type-B, the time tracker block 134 may estimatethe symbol timing error 144 by detecting timing of a beginning of eachcharacter. In one approach, the time tracker block 134 may then adjustthe symbol timing 148 by incrementing initial symbol timing 146 by afixed bit duration. In another approach, the time tracker block 134 maycompare a location of a low-to-high or high-to-low transition in thereceived signal 118 with an ideal location of a transition to estimatethe symbol timing error 144. In this approach, the time tracker block134 may then adjust the symbol timing 148 by adding or subtracting theestimated symbol timing error 144 from the sample counter 142.

It should be noted that for type-B, time tracking may not be needed ifcharacter acquisition is capable of providing symbol timing 148 with afine resolution, rather than a coarse resolution of a bit duration, forexample. In other words, type-B may not need time tracking becausecharacter acquisition may be designed such that it adjusts bitboundaries itself.

Type-F uses the Manchester code as a line code. In the Manchester code,there is a high-to-low transition or a low-to-high transition in everybit. By estimating the timing of a transition relative to the start of abit duration, the time tracker block 134 can estimate bit boundaryerrors and adjust the bit boundary for the following bit accordingly.

For NFC type-F, the time tracker block 134 may estimate the symboltiming error 144 by comparing a location of a low-to-high or ahigh-to-low transition in a received signal 118 with an ideal locationof a transition. The time tracker block 134 may adjust the symbol timing148 by adding or subtracting the estimated symbol timing error 144 fromthe sample counter 142.

FIG. 2 is a flow diagram illustrating a method 200 for timing recoveryin NFC. The method 200 may be performed by a target NFC device 104. Thetarget NFC device 104 may receive 202 a signal 118 from an initiator NFCdevice 102. The received signal 118 may be modulated according to one ofNFC type-A, type-B or type-F.

The target NFC device 104 may analyze 204 the signal 118 to estimate asymbol timing error 144. For example, the time tracker block 134 canestimate bit boundary errors based on the output of the ADC 128 or theslicer 130.

In one configuration, the target NFC device 104 may estimate the symboltiming error 144 by comparing a location of a low-to-high or ahigh-to-low transition in the received signal 118 with an ideal locationof a transition. For example, based on initial symbol timing 146provided by the acquisition block 132, the target NFC device 104 maydetermine the ideal location of a transition.

The target NFC device 104 may accumulate samples during differentperiods of a bit duration. For example, the target NFC device 104 mayobtain samples of the bit stream output of the slicer 130. By comparingthe samples to the ideal location of a transition, the target NFC device104 may determine the symbol timing error 144.

The target NFC device 104 may adjust 206 symbol timing 148 to correctfor the symbol timing error 144. The target NFC device 104 may adjust206 the symbol timing 148 by incrementing the initial symbol timing 146.

In one configuration, the target NFC device 104 may adjust 206 thesymbol timing 148 by adding or subtracting the estimated symbol timingerror 144 from a sample counter 142. In this configuration, the samplecounter 142 may count the samples from the start of symbol (as indicatedby the initial symbol timing 146, for instance). In anotherconfiguration, the target NFC device 104 may adjust 206 the symboltiming 148 by incrementing initial symbol timing 146 by a fixed bitduration.

FIG. 3 is a block diagram illustrating an NFC system 300. The NFC system300 includes a plurality of NFC tags 350A-350D, a plurality of NFCreaders 352A-352C and an application server 356.

The NFC tags 350A-350D may each be associated with a particular objectfor a variety of purposes including, but not limited to, trackinginventory, tracking status, location determination and assemblyprogress. The NFC tags 350A-350D may be active devices that includeinternal power sources or passive devices that derive power from the NFCreaders 352A-352C.

Although FIG. 3 shows only four NFC tags and three NFC readers, thepresent disclosure is not limited thereto. In one configuration, the NFCtags 350A-350D may be implemented in accordance with the target NFCdevice 104 described in connection with FIG. 1. In one configuration,the readers 352A-352C may be implemented in accordance with theinitiator NFC device 102 described in connection with FIG. 1.

Each NFC reader 352A-352C wirelessly communicates data with one or moreNFC tags 350A-350D within its coverage area. For example, the NFC tags350A and 350B may be within a coverage area of the NFC reader 352A, theNFC tags 350B and 350C may be within a coverage area of the NFC reader352B, and the NFC tags 350C and 350D may be within a coverage area ofthe NFC reader 352C. In one configuration, the RF communicationmechanism between the NFC readers 352A-352C and the NFC tags 350A-350Dis a backscatter technique. In this configuration, the NFC readers352A-352C request data from the NFC tags 350A-350D via an RF signal, andthe RF tags 350A-350D respond with the requested data by modulating andbackscattering the RF signal provided by the NFC readers 352A-352C.

In another configuration, the RF communication mechanism is aninductance technique whereby the NFC readers 352A-352C magneticallycouple to the NFC tags 350A-350D via an RF signal to access the data onthe NFC tags 350A-350D. In either configuration, the NFC tags 350A-350Dprovide the requested data to the NFC readers 352A-352C on the same RFcarrier frequency as the RF signal.

In this manner, the NFC readers 352A-352C collect data from each of theNFC tags 350A-350D within its coverage area. The collected data is thenconveyed to the application server 356 via a wired or wirelessconnection 354 and/or via possible communication mechanism, for example,a peer-to-peer communication connection. In addition, and/or in thealternative, the application server 356 may provide data to one or moreof the NFC tags 350A-350D via the associated NFC readers 352A-352C. Suchdownloaded information is application dependent and may vary greatly.Upon receiving the downloaded data, the NFC tag can store the data in anon-volatile memory therein.

In another configuration, the NFC readers 352A-352C may optionallycommunicate data on a peer-to-peer basis such that each NFC reader doesnot need a separate wired or wireless connection 354 to the applicationserver 356. For example, the NFC reader 352A and the NFC reader 352B maycommunicate on a peer-to-peer basis utilizing a back scatter technique,a WLAN technique, and/or any other wireless communication technique. Inthis instance, the NFC reader 352B may not include a wired or wirelessconnection 354 to the application server 356. In configurations in whichcommunications between the NFC reader 352A-352C and the applicationserver 356 are conveyed through the wired or wireless connection 354,the wired or wireless connection 354 may utilize any one of a pluralityof wired standards (e.g., Ethernet and fire wire) and/or wirelesscommunication standards (e.g., IEEE 802.11x and Bluetooth).

As one of ordinary skill in the art will appreciate, the NFC system ofFIG. 3 may be expanded to include a multitude of NFC readers 352A-352Cdistributed throughout a desired location (for example, a building oroffice site) where the NFC tags may be associated with equipment,inventory and/or personnel. In addition, it should be noted that theapplication server 356 may be coupled to another server and/or networkconnection to provide wide area network coverage.

FIG. 4 is a block diagram illustrating an exemplary schematic of an NFCsystem 400 including a transceiver and a remote unit. The NFC system 400includes an NFC transceiver 460 and a remote unit 472 such as an NFCtag. The NFC transceiver 460 may include a voltage power source 466, anNFC transceiver control circuit 468 and a transmitter circuit 464. TheNFC transceiver control circuit 468 is powered by the voltage source466, and connected to one or more transceiver loops 462.

The transceiver loops 462 are hereinafter interchangeably used withcoils or loop antennae. The coils and loop antenna may be made ofconductive material, for example, an electromagnetic coil, through whichan alternating current (AC) 470 can flow. The transceiver loops 462 maybe circular, oval, and the like, although other sizes and shapes arepossible. The AC current 470 flowing through the transceiver loops 462can result in transmitting magnetic energy or magnetic flux 480 atvarious frequencies (e.g., about 100 kHz to about 40 MHz). Thewavelength of the emitted frequencies may be much longer than the sizeof loops 462 on the NFC transceiver 460.

The remote unit 472 includes a receiver circuit 474 and a remote unitcontrol circuit 476. If the remote unit 472 is close enough to the NFCtransceiver 460, the magnetic flux 480 from the transceiver 460 can getAC coupled onto one or more remote unit loops 478 of conductivematerial, which can be an unpowered device (i.e., without a battery orother means of applying continuous power) having the electromagneticcoil and remote unit control circuit 476. An oscillating AC current 482flowing in alternating directions in the remote unit control circuit 476can be rectified by a rectifying diode in the remote unit controlcircuit 476, which can cause a voltage to be built up across a bypasscapacitor in the remote unit control circuit 476. Once the bypasscapacitor has built up a sufficient voltage, the remote unit controlcircuit 476 can become powered up and operational. By receiving coupledand modulated AC signal from the NFC transceiver 460, the remote unit472 can receive and detect information (e.g., commands) from the NFCtransceiver 460.

Once operational, the remote unit control circuit 476 may also sendsignals back to the NFC transceiver 460 by changing the impedance seenby the remote unit loops 478. This can be accomplished by shunting oropening the remote unit loops 478 with, for example, a switch. If theremote unit 472 is close enough to the NFC transceiver 460, themodulated electromagnetic field generated by the remote unit loops 478in the remote unit 472 can be coupled back onto the reader loops 462 ofthe NFC transceiver 460. The signals sent back to the NFC transceiver460 can be slow and on the order of 100 bits of data, and provideinformation back to the transceiver 460 such as the serial number ormodel number of the device to which the remote unit 472 is attached,credit card number, personal identification information, security codesand passwords, and the like.

FIG. 5 illustrates an exemplary diagram of a modified-Miller codepattern, an NRZ (non-return-to-zero) code pattern and a Manchester codepattern. NRZ and Manchester codes are relatively straightforwardcompared to a modified-Miller code. Three waveform patterns areillustrated in FIG. 5. Waveform pattern 575 represents a modified-Millercode for type-A. Waveform pattern 577 represents an NRZ code for type-B.Waveform pattern 579 represents a Manchester code for type-F. Pattern 1is generally used to represent bit 1. Pattern 0 is used to represent bit0 for type-B and type-F. For type-A, the pattern for bit 0 is eitherpattern 0A or 0B, depending on the previous bit. If the previous bit is1, then pattern 0A is used to transmit bit 0; otherwise, pattern 0B isused.

The NFC protocol poses a few unique challenges to wirelesscommunication. First, the signal amplitude of NFC may be severelydistorted by an RF subsystem. This is because the signal dynamic rangeof NFC may be relatively large at a receive antenna 122. As such, aconventional automatic gain control (AGC) may not perform well for NFC.Second, an NFC type-B signal may contain a long sequence of high level(or low level) values, which makes the traditional DC offsetcancellation technique impracticable or unworkable.

In one configuration, signal amplitude is extracted in the RF subsystemand fed to an analog-to-digital converter (ADC) 128, followed byoperations by the acquisition block 132 and decoder block 136 onmulti-bit ADC output samples. A time tracker block 134 may estimate thesymbol timing error 144 and adjust the symbol timing 148. The decoderblock 136 could be implemented by applying a plurality of matchedfilters (e.g., two matched filters, one for Pattern 0 and the other forPattern 1, when decoding Manchester-coded signal) to ADC output afterremoving direct current (DC) components.

Another configuration performs slicing (by a slicer 130, for example) inthe RF subsystem and runs the acquisition block 132, time tracking block134 and decoder block 136 on a single-bit slicer output. In thiscontext, slicing may refer to converting an input sequence of M-bitsamples into an output sequence of N-bit samples (where M and N arepositive integer numbers) and removing a time-varying DC component fromthe input sequence. The decoder block 136 could be implemented usingbinary matched filtering (meaning input and filter coefficients arebinary symbols).

FIG. 6 illustrates examples of signal waveforms that are processedinside the NFC receiver 106 of FIG. 1. The signal waveforms include areceived passband signal waveform 680, an envelope detector outputsignal waveform 682, and a slicer output signal waveform 684.

The received passband signal waveform 680 may indicate the modulatedsymbols received and outputted by the receive antenna 122. As shown inFIG. 6, the received passband signal waveform 680 includes at least twosymbols: the high amplitude symbol 686 (denoted as “A”) and lowamplitude symbol 688 (denoted as “B”).

The envelope detector output signal waveform 682 is the correspondingoutput from the envelope detector 124 as shown in FIG. 1. The envelopedetector output signal waveform 682 includes at least two demodulatedsymbols 690 and 692 corresponding to the symbols 686 and 688,respectively.

The slicer output signal waveform 684 denotes the corresponding outputfrom the slicer 130. The slicer output signal waveform 684 includes atleast two symbols (or bits) 694 and 696 (denoted as “1” and “0”)corresponding to the symbols 690 and 692, respectively. The sliceroutput signal waveform 684 is sent to the acquisition block 132, thetime tracker block 134 and the decoder 136. The time tracker block 134may estimate the symbol timing error 144 and adjust the symbol timing148 based on the slicer output signal waveform 684.

FIG. 7 is a block diagram illustrating symbol timing 748 for NFC type-A.Specifically, FIG. 7 illustrates the slicer 130 output observed by thetime tracker block 134, the sum of the left side and the right side of apause, and symbol timing 148 when the modem clock is an ideal clock 731,a faster clock 733, or a slower clock 735. FIG. 7 shows that thedifference between the sum of the left side of a pause and the sum ofthe right side of a pause is proportional to the timing offset of thecurrent bit.

In NFC type-A, a bit may be split into four quarters. Therefore, a bitmay have a first quarter (Q1), a second quarter (Q2) a third quarter(Q3) and a fourth quarter (Q4).

For bit 0B, the sum of the left-side of a pause is denoted by sumLeftQ1(the sum of the right-aligned portion of Q4 plus the sum of the firsthalf of Q1) and the sum of the right-side of a pause by sumRightQ1 (sumof the left-aligned portion of Q2 plus sum of the other half of Q1). Thedifference is defined as diff=sumLeftQ1−sumRightQ1.

Similarly, for bit 1, the difference is defined asdiff=sumLeftQ3−sumRightQ3. From this example, it is observable that:diff is zero for the ideal clock 731 case; the next symbol timing 148pulse should occur after 256 cycles (for 106 kbps packets assumingsampling rate is 27.12 MHz) from the previous pulse.

For the faster clock 733 case, diff is positive and is twice the timingoffset. The next symbol timing 148 pulse should occur after 256+0.5*diffcycles from the previous pulse.

For the slower clock 735 case, diff is negative and is twice the timingoffset. The next symbol timing 148 pulse should occur after 256+0.5*diffcycles from the previous pulse.

As described above, symbol timing 148 pulses may be generated at thedesired timing by subtracting 0.5*diff from a sample counter 142 at themoment of correction/adjustment and by generating symbol timing 148pulses when the sample counter 142 reaches 0, assuming a modulo-256counter 142 (for 106 kbps packets). The following discussion illustratesthe timing at which a sample counter 142 should be adjusted. Note that atarget decoder 136 can generate a decoded bit after Q3 because Q4 isirrelevant for decoding.

FIG. 8 illustrates the adjustment timing and the behavior of a samplecounter 142 for the faster clock 733 case for NFC type-A. The symboltiming 848 for a bit 0B input waveform 884 a is shown with acorresponding sample counter 842 a. Similarly, the symbol timing 848 fora bit 1 input waveform 884 b is shown with a corresponding samplecounter 842 b. Depending on the decoded bit, a sample counter 842 may beadjusted as follows.

If the decoded bit corresponds to bit 0A (i.e., the current decoded bitis zero and the previous decoded bit is one), then the time trackerblock 134 does not make any adjustment. If the decoded bit correspondsto bit 0B (i.e., the current decoded bit is zero and the previousdecoded bit is also zero), then the time tracker block 134 applies thetiming adjustment (−0.5*diff, as determined according to FIG. 7) to thesample counter 142 at the end of Q3. In the case of a faster clock 733,there is a negative adjustment in the sample counter 142 because diff ispositive.

If the decoded bit corresponds to bit 1, then the time tracker block 134applies the timing adjustment (−0.5*diff) to the sample counter 142 atthe end of the accumulation period for sumRightQ3.

FIG. 9 illustrates the adjustment timing and the behavior of a samplecounter 142 for the slower clock 735 case for NFC type-A. The symboltiming 948 for a bit 0B input waveform 984 a is shown with acorresponding sample counter 942 a. Similarly, the symbol timing 948 fora bit 1 input waveform 984 b is shown with a corresponding samplecounter 942 b. Depending on the decoded bit, a sample counter 942 may beadjusted as follows. Depending on the decoded bit, a sample counter 942may be adjusted as follows.

If the decoded bit corresponds to bit 0A (i.e., the current decoded bitis zero and the previous decoded bit is one), then the time trackerblock 134 does not make any adjustment. If the decoded bit correspondsto bit 0B (i.e., the current decoded bit is zero and the previousdecoded bit is also zero), then the time tracker block 134 applies thetiming adjustment (−0.5*diff, as determined according to FIG. 7) to thesample counter 142 at the end of Q3. In the case of a slower clock 735,there is a positive adjustment in the sample counter 142 because diff isnegative.

If the decoded bit corresponds to bit 1, then the time tracker block 134applies the timing adjustment (−0.5*diff) to the sample counter 142 atthe end of the accumulation period for sumRightQ3.

FIG. 10 is a block diagram illustrating a configuration of a timetracker block 1034 when modulation is performed in accordance with NFCtype-A. In this configuration, the type-A time tracker block 1034includes four accumulators 1037 a-d, two timing error estimators 1039a-b, a sample counter 1042 and an adjustment timing control block 1043.

The accumulator 1037 a (whose output is denoted by sumQ1Left)accumulates a subset of input samples 1045 on the left-side of thecenter of the first quarter of a bit duration. The accumulator 1037 b(whose output is denoted by sumQ1Right) accumulates a subset of inputsamples 1045 on the right-side of the center of the first quarter of abit duration, and similarly for the other two accumulators 1037 c-dwhose output is denoted by sumQ3Left and sumQ3Right.

The pair of sumQ1Left and sumQ1Right is coupled to the timing errorestimator 1039 a for bit 0B block, which may compute and output theadjustment for the sample count (denoted by adjustmentBit0B) using aformula adjustmentBit0B=(sumQ1Right−sumQ1Left)/2 followed by therounding to the nearest integer operation. Similarly, the pair ofsumQ3Left and sumQ3Right is coupled to the timing error estimator 1039 bfor bit 1 block, which may compute and output the adjustment for thesample count (denoted by adjustmentBit1) using a formulaadjustmentBit1=(sumQ3Right−sumQ3Left)/2 followed by the rounding to thenearest integer operation. The adjustmentBit0B and adjustmentBit1 may beconstrained to a specified range (not shown in the block diagram).

Depending on the adjusmentSelect signal generated by the adjustmenttiming control block 1043, one of the three values (adjustmentBit0B,adjustmentBit1 and zero) is selected by a multiplexer 1047. The outputof the multiplexer 1047 is added by one by the adder 1049 to produce theincrement signal.

The sample counter 1042 increments the sample count at each clock cycleusing the increment signal as the (variable) increment step size. Thesample counter 1042 is reset every time the sample count exceeds thenumber of samples per bit. The symbol timing 1048 signal has the valueof one when the sample count is equal to the number of samples per bit,and the value of zero otherwise.

The adjustment timing control block 1043 is coupled to the decoded bitand the previous decoded bit, which may be generated by a decoder 136.The output of the adjustment timing control block 1043, denoted byadjustmentSelect, controls the source and timing of the adjustment forthe increment step size of the sample counter 1042.

The adjustmentSelect signal may be generated as follows. In a firstcase, it may be set to zero if the sample count equals 0.75*the numberof samples per bit, the decoded bit is zero, and the previous decodedbit is also zero. In a second case, it may be set to one if the samplecount equals the last sample index of the accumulation period forsumQ3Right, and the decoded bit is one. In a third case, it may be setto two if neither of the above two conditions is satisfied.

In this configuration, a decoder 136 should complete and provide thedecoded bit to the time tracker block 1034 at the end of the thirdquarter of a bit duration, which is possible because the fourth quarteris not needed in decoding.

FIG. 11 is a flow diagram illustrating one possible method 1100 forestimating symbol timing error 144 where modulation is performed inaccordance with NFC type-A. The method 1100 may be performed by a targetNFC device 104. The target NFC device 104 may receive 1102 a signal 118from an initiator NFC device 102. The received signal 118 may bemodulated according to NFC type-A.

The target NFC device 104 may decode 1104 a bit from the signal 118. Forexample, a decoder 136 may decode the bit in a bit stream. The targetNFC device 104 may feed back the decoded bit to the time tracker 134.Alternatively, the time tracker 134 may perform decoding itself.

The target NFC device 104 may compare 1106 the location of a pause(i.e., a modulated portion of a bit) in the received signal 118 with theideal location of a pause corresponding to the decoded bit. Thedifference of the two is the (estimated) symbol timing error 144.

The symbol timing 148 for the next bit duration may be advanced orretarded 1108 by, for example, adding or subtracting the symbol timingerror 144 to/from a sample counter 142. For example, a sample counter142 may count from 0 to N (e.g., 128). When it reaches N, indicating abit boundary, the counter 142 may reset to 0 and count from 0 to Nagain. Adding or subtracting the symbol timing error 144 to/from thesample counter 142 causes the counter 142 to reach N later or earlier.

FIG. 12 is a block diagram illustrating symbol timing 1248 for NFCtype-F. Manchester coding used in type-F packets ensures that there is alow-to-high or high-to-low transition in the middle of a packet. Timetracking may be performed by monitoring the timing of a transition. InFIG. 12, the current bit is depicted with a first half (H1) and a secondhalf (H2).

It can be difficult to recognize an actual low-to-high (or high-to-low)transition from a false low-to-high (or high-to-low) transition createdby noise. Rather than making a sample-by-sample comparison to determinea transition, a certain number of samples may be accumulated around theideal transition point. This is designated in FIG. 12 by sumH1 andsumH2. The timing of a transition can be estimated by comparing the sumof the first half, denoted by sumH1, and the sum of the second half,denoted by sumH2. FIG. 12 illustrates that a timing offset is related tosumH1 and sumH2 as follows.

In the ideal clock 1231 case, sumH1+sumH2=accum_length. In this case,accum_length is the accumulation duration each for sumH1 and sumH2.

In the faster clock 1233 case (i.e., positive timing offset), the timingoffset=sumH1−(accum_length−sumH2) if sumH1 is greater than or equal tosumH2. Otherwise, timing offset=(accum_length−sumH1)−sumH2 if sumH1 isless than sumH2.

In the slower clock 1235 case (i.e., negative timing offset), the timingoffset=sumH1−(accum_length−sumH2) if sumH1 is greater than or equal tosumH2. Otherwise, timing offset=(accum_length−sumH1)−sumH2 if sumH1 isless than sumH2.

The above relations may be expressed according to equation (1).

$\begin{matrix}{{{timing}\mspace{14mu}{offset}} = \left\{ \begin{matrix}{{{{sumH}\; 1} + {{sumH}\; 2} - {accum\_ length}},{{{if}\mspace{14mu}{sumH}\; 1} \geq {{sumH}\; 2}}} \\{{- \left( {{{sumH}\; 1} + {{sumH}\; 2} - {accum\_ length}} \right)},{{{if}\mspace{14mu}{sumH}\; 1} < {{sumH}\; 2}}}\end{matrix} \right.} & (1)\end{matrix}$

FIG. 13 illustrates the behavior of the sample counter 1342 and symboltiming 1348 in the faster clock 1233 case for NFC type-F. The symboltiming 1348 for a bit 0B input waveform 1384 a is shown with acorresponding sample counter 1342 a. Similarly, the symbol timing 1348for a bit 1 input waveform 1384 b is shown with a corresponding samplecounter 1342 b.

The estimated timing offset may be compensated for by subtracting thetiming offset from a sample counter 1342 at the end of the sumH2accumulation period. More specifically, a sample counter 1342 may be setto the previous count value −timing offset +1, where the timing offsethas been provided in equation (1). The adjustment to the sample counter1342 adjusts the timing of the next symbol timing 1348 pulse.

In this example, the sample counter 1342 counts from 0 to 128. In thefaster clock 1233 case, the timing offset is positive. Therefore, timetracker block 134 may produce a negative adjustment by subtracting thetiming offset from the sample counter 1342 at the end of the sumH2accumulation period.

FIG. 14 illustrates the behavior of the sample counter 1442 and symboltiming 1448 in the slower clock 1235 case for NFC type-F. The symboltiming 1448 for a bit 0 input waveform 1484 a is shown with acorresponding sample counter 1442 a. Similarly, the symbol timing 1448for a bit 1 input waveform 1484 b is shown with a corresponding samplecounter 1442 b.

As described above, the estimated timing offset may be compensated forby subtracting the timing offset from a sample counter 1442 at the endof the sumH2 accumulation period. More specifically, a sample counter1442 may be set to the previous count value−timing offset+1, where thetiming offset has been provided in equation (1). The adjustment to thesample counter 1442 adjusts the timing of the next symbol timing 1448pulse.

In this example, the sample counter 1442 counts from 0 to 128. In theslower clock 1235 case, the timing offset is negative. Therefore, timetracker block 134 may produce a positive adjustment by subtracting thetiming offset to the sample counter 1442 at the end of the sumH2accumulation period.

FIG. 15 is a block diagram illustrating a configuration of a timetracker block 1534 when modulation is performed in accordance with NFCtype-F. In this configuration, the type-F time tracker block 1534includes two accumulators 1537 a-b, two timing error estimators 1539a-b, a sample counter 1542, an internal decoder 1551 and an adjustmenttiming control block 1543.

The accumulator 1537 a (whose output is denoted by sumH1) accumulates asubset of input samples 1545 on the left-side of the center of a bitduration. The accumulator 1537 b (whose output is denoted by sumH2)accumulates a subset of input samples 1545 on the right-side of thecenter of a bit duration.

The pair of sumH1 and sumH2 is coupled to the timing error estimators1539 a-b and the internal decoder 1551. The timing error estimator 1539a for bit 0 block may compute and output the adjustment for the samplecount (denoted by adjustmentBit0) using a formulaadjustmentBit0=sumH1+sumH2−N, where N denotes the accumulation durationfor each accumulator 1537. Similarly, the timing error estimator 1539 bfor bit 1 block may compute and output the adjustment for the samplecount (denoted by adjustmentBit1) using a formulaadjustmentBit1=N−sumH1−sumH2. The adjustmentBit0 and adjustmentBit1 maybe constrained to a specified range (not shown in the block diagram).

Depending on the adjusmentSelect signal generated by the adjustmenttiming control block 1543, one of the three values (adjustmentBit0,adjustmentBit1 and zero) is selected by a multiplexer 1547. The outputof the multiplexer 1547 is added by one by the adder 1549 to produce theincrement signal.

The sample counter 1542 increments the sample count at each clock cycleusing the increment signal as the (variable) increment step size. Thesample counter 142 is reset every time the sample count is equal to thenumber of samples per bit. The symbol timing 1548 signal has the valueof one when the sample count is equal to the number of samples per bit,and the value of zero otherwise.

The pair of sumH1 and sumH2 may also be coupled to the internal decoder1551. The internal decoder 1551 may output the decoded bit using aformula, decoded bit=0 if sumH1<=sumH2 and decoded bit=1 if sumH1>sumH2.

The decoded bit and the sample count may be coupled to the input of theadjustment timing control block 1543, which controls the source andtiming of the adjustment for the increment step size of the samplecounter 1542.

The adjustmentSelect signal may be generated as follows. In a firstcase, it may be set to zero if the sample count equals the last sampleindex of the accumulation period for sumH2, and the decoded bit is zero.In a second case, it may be set to one if the sample count equals thelast sample index of the accumulation period for sumH2, and the decodedbit is one. In a third case, it may be set to two if neither of theabove two conditions is satisfied.

In this configuration, the internal decoder 1551 must complete andprovide the decoded bit to the adjustment timing control block 1543 atthe end of the accumulation period for sumH2.

FIG. 16 is a flow diagram illustrating one possible method 1600 forestimating symbol timing error 144 where modulation is performed inaccordance with NFC type-F. The method 1600 may be performed by a targetNFC device 104. The target NFC device 104 may receive 1602 a signal 118from an initiator NFC device 102. The received signal 118 may bemodulated according to NFC type-F.

The target NFC device 104 may decode 1604 a bit from the signal 118. Forexample, a decoder 136 may decode the bit in a bit stream. The targetNFC device 104 may feed back the decoded bit to the time tracker 134.Alternatively, the time tracker 134 may perform decoding itself.

The target NFC device 104 may compare 1606 the location of a low-to-highor a high-to-low transition in the received signal 118 with the ideallocation of a transition, which is the center of a bit duration. (Pleaserefer to FIG. 12 for an example of an ideal clock 1231, a faster clock1233, and a slower clock 1235.) The difference of the two is the(estimated) symbol timing error 144.

Regarding step 1606, it can be difficult to recognize an actuallow-to-high (or high-to-low) transition from a false low-to-high (orhigh-to-low) transition created by noise. Rather than making asample-by-sample comparison, a certain number of samples may beaccumulated around the ideal transition point. This is designated bysumH1 and sumH2 (which are shown in FIG. 12 and which were discussedpreviously). The comparison of a low-to-high or a high-to-low transitionin a received signal 118 with the ideal location of a transition (step1606) may be performed by comparing sumH1 and sumH2 (see equation (1)discussed above).

The symbol timing 148 for the next bit duration may be advanced orretarded 1608. For example, the target NFC device 104 may add orsubtract the symbol timing error 144 to/from a sample counter 142.

FIG. 17 is a flow diagram illustrating one possible method 1700 forestimating symbol timing error 144 where modulation is performed inaccordance with NFC type-B. The method 1700 may be performed by a targetNFC device 104. The target NFC device 104 may receive 1702 a signal 118from an initiator NFC device 102. The received signal 118 may bemodulated according to NFC type-B.

The target NFC device 104 may detect 1704 the timing of each character.For example, an acquisition block 132 may detect 1704 the beginning ofeach character. Each character may include 10 bits: one bit indicatingthe start of a character, eight information bits, and one bit indicatingthe end of a character.

The initial symbol timing 146 may be incremented 1706 by a (fixed) bitduration to use it as the symbol timing 148 for each subsequent bit inthe same character.

FIG. 18 is a flow diagram illustrating another possible method 1800 forestimating symbol timing error 144 where modulation is performed inaccordance with NFC type-B. The method 1800 may be performed by a targetNFC device 104. The target NFC device 104 may receive 1802 a signal 118from an initiator NFC device 102. The received signal 118 may bemodulated according to NFC type-B.

The target NFC device 104 may detect 1804 the timing of each character.For example, an acquisition block 132 may detect 1804 the beginning ofeach character. As indicated above, each character may include 10 bits:one bit indicating the start of a character, eight information bits, andone bit indicating the end of a character.

The target NFC device 104 may decode 1806 a bit from the signal 118. Forexample, a decoder 136 may decode the bit in a bit stream. The targetNFC device 104 may feed back decoded bit to the time tracker 134.Alternatively, the time tracker 134 may perform decoding itself.

The target NFC device 104 may compare 1808 the location of a low-to-highor high-to-low transition in a received signal 118 with the ideallocation of a transition (which is exactly the bit boundary). Thedifference of the two is the (estimated) symbol timing error 144.

The symbol timing 148 for the next bit duration may be advanced orretarded 1810. For example, the target NFC device 104 may add orsubtract the symbol timing error 144 to/from a sample counter 142.

FIG. 19 illustrates certain components that may be included within anelectronic device 1904. The electronic device 1904 may be an accessterminal, a mobile station, a user equipment (UE), etc. For example, theelectronic device 1904 may be the initiator NFC device 102 of FIG. 1.

The electronic device 1904 includes a processor 1903. The processor 1903may be a general purpose single- or multi-chip microprocessor (e.g., anAdvanced RISC (Reduced Instruction Set Computer) Machine (ARM)), aspecial purpose microprocessor (e.g., a digital signal processor (DSP)),a microcontroller, a programmable gate array, etc. The processor 1903may be referred to as a central processing unit (CPU). Although just asingle processor 1903 is shown in the electronic device 1904 of FIG. 19,in an alternative configuration, a combination of processors (e.g., anARM and DSP) could be used.

The electronic device 1904 also includes memory 1905 in electroniccommunication with the processor (i.e., the processor can readinformation from and/or write information to the memory). The memory1905 may be any electronic component capable of storing electronicinformation. The memory 1905 may be configured as random access memory(RAM), read-only memory (ROM), magnetic disk storage media, opticalstorage media, flash memory devices in RAM, on-board memory includedwith the processor, EPROM memory, EEPROM memory, registers and so forth,including combinations thereof.

Data 1907 a and instructions 1909 a may be stored in the memory 1905.The instructions may include one or more programs, routines,sub-routines, functions, procedures, code, etc. The instructions mayinclude a single computer-readable statement or many computer-readablestatements. The instructions 1909 a may be executable by the processor1903 to implement the methods disclosed herein. Executing theinstructions 1909 a may involve the use of the data 1907 a that isstored in the memory 1905. When the processor 1903 executes theinstructions 1909, various portions of the instructions 1909 b may beloaded onto the processor 1903, and various pieces of data 1907 b may beloaded onto the processor 1903.

The electronic device 1904 may also include a transmitter 1911 and areceiver 1913 to allow transmission and reception of signals to and fromthe electronic device 1904 via an antenna 1917. The transmitter 1911 andreceiver 1913 may be collectively referred to as a transceiver 1915. Theelectronic device 1904 may also include (not shown) multipletransmitters, multiple antennas, multiple receivers and/or multipletransceivers.

The electronic device 1904 may include a digital signal processor (DSP)1921. The electronic device 1904 may also include a communicationsinterface 1923. The communications interface 1923 may allow a user tointeract with the electronic device 1904.

The various components of the electronic device 1904 may be coupledtogether by one or more buses, which may include a power bus, a controlsignal bus, a status signal bus, a data bus, etc. For the sake ofclarity, the various buses are illustrated in FIG. 19 as a bus system1919.

In the above description, reference numbers have sometimes been used inconnection with various terms. Where a term is used in connection with areference number, this may be meant to refer to a specific element thatis shown in one or more of the Figures. Where a term is used without areference number, this may be meant to refer generally to the termwithout limitation to any particular Figure.

The term “determining” encompasses a wide variety of actions and,therefore, “determining” can include calculating, computing, processing,deriving, investigating, looking up (e.g., looking up in a table, adatabase or another data structure), ascertaining and the like. Also,“determining” can include receiving (e.g., receiving information),accessing (e.g., accessing data in a memory) and the like. Also,“determining” can include resolving, selecting, choosing, establishingand the like.

The phrase “based on” does not mean “based only on,” unless expresslyspecified otherwise. In other words, the phrase “based on” describesboth “based only on” and “based at least on.”

The term “processor” should be interpreted broadly to encompass ageneral purpose processor, a central processing unit (CPU), amicroprocessor, a digital signal processor (DSP), a controller, amicrocontroller, a state machine, and so forth. Under somecircumstances, a “processor” may refer to an application specificintegrated circuit (ASIC), a programmable logic device (PLD), a fieldprogrammable gate array (FPGA), etc. The term “processor” may refer to acombination of processing devices, e.g., a combination of a digitalsignal processor (DSP) and a microprocessor, a plurality ofmicroprocessors, one or more microprocessors in conjunction with adigital signal processor (DSP) core, or any other such configuration.

The term “memory” should be interpreted broadly to encompass anyelectronic component capable of storing electronic information. The termmemory may refer to various types of processor-readable media such asrandom access memory (RAM), read-only memory (ROM), non-volatile randomaccess memory (NVRAM), programmable read-only memory (PROM), erasableprogrammable read-only memory (EPROM), electrically erasable PROM(EEPROM), flash memory, magnetic or optical data storage, registers,etc. Memory is said to be in electronic communication with a processorif the processor can read information from and/or write information tothe memory. Memory that is integral to a processor is in electroniccommunication with the processor.

The terms “instructions” and “code” should be interpreted broadly toinclude any type of computer-readable statement(s). For example, theterms “instructions” and “code” may refer to one or more programs,routines, sub-routines, functions, procedures, etc. “Instructions” and“code” may comprise a single computer-readable statement or manycomputer-readable statements.

The functions described herein may be implemented in software orfirmware being executed by hardware. The functions may be stored as oneor more instructions on a computer-readable medium. The terms“computer-readable medium” or “computer-program product” refers to anytangible storage medium that can be accessed by a computer or aprocessor. By way of example, and not limitation, a computer-readablemedium may include RAM, ROM, EEPROM, CD-ROM or other optical diskstorage, magnetic disk storage or other magnetic storage devices, or anyother medium that can be used to carry or store desired program code inthe form of instructions or data structures and that can be accessed bya computer. Disk and disc, as used herein, includes compact disc (CD),laser disc, optical disc, digital versatile disc (DVD), floppy disk andBlu-ray® disc where disks usually reproduce data magnetically, whilediscs reproduce data optically with lasers. It should be noted that acomputer-readable medium may be tangible and non-transitory. The term“computer-program product” refers to a computing device or processor incombination with code or instructions (e.g., a “program”) that may beexecuted, processed or computed by the computing device or processor. Asused herein, the term “code” may refer to software, instructions, codeor data that is/are executable by a computing device or processor.

Software or instructions may also be transmitted over a transmissionmedium. For example, if the software is transmitted from a website,server, or other remote source using a coaxial cable, fiber optic cable,twisted pair, digital subscriber line (DSL), or wireless technologiessuch as infrared, radio, and microwave, then the coaxial cable, fiberoptic cable, twisted pair, DSL, or wireless technologies such asinfrared, radio, and microwave are included in the definition oftransmission medium.

The methods disclosed herein comprise one or more steps or actions forachieving the described method. The method steps and/or actions may beinterchanged with one another without departing from the scope of theclaims. In other words, unless a specific order of steps or actions isrequired for proper operation of the method that is being described, theorder and/or use of specific steps and/or actions may be modifiedwithout departing from the scope of the claims.

Further, it should be appreciated that modules and/or other appropriatemeans for performing the methods and techniques described herein, suchas those illustrated by FIG. 2, FIG. 11 and FIGS. 16-18, can bedownloaded and/or otherwise obtained by a device. For example, a devicemay be coupled to a server to facilitate the transfer of means forperforming the methods described herein. Alternatively, various methodsdescribed herein can be provided via a storage means (e.g., randomaccess memory (RAM), read only memory (ROM), a physical storage mediumsuch as a compact disc (CD) or floppy disk, etc.), such that a devicemay obtain the various methods upon coupling or providing the storagemeans to the device. Moreover, any other suitable technique forproviding the methods and techniques described herein to a device can beutilized.

It is to be understood that the claims are not limited to the preciseconfiguration and components illustrated above. Various modifications,changes and variations may be made in the arrangement, operation anddetails of the systems, methods, and apparatus described herein withoutdeparting from the scope of the claims.

What is claimed is:
 1. A method for inductively-coupled communications,comprising: receiving a signal from an inductively coupled communicationdevice; analyzing the signal to estimate a symbol timing error,comprising: summing multiple samples in a first portion of the signalfor a bit to form a first sum; summing multiple samples in a secondportion of the signal for the bit to form a second sum; determining thesymbol timing error based on at least the first sum and the second sum;and adjusting symbol timing to correct for the symbol timing error byadding or subtracting the estimated symbol timing error from a samplecounter that counts samples from a start of a symbol.
 2. The method ofclaim 1, wherein estimating the symbol timing error comprises comparinga location of a pause, a low-to-high or a high-to-low transition in thereceived signal with an ideal location of a pause or a transition. 3.The method of claim 1, wherein estimating the symbol timing errorcomprises detecting timing of a beginning of each character.
 4. Themethod of claim 1, wherein estimating the symbol timing error is basedon an output of one or more accumulators that accumulate samples duringdifferent periods in a bit duration.
 5. The method of claim 1, whereinthe summing multiple samples in a first portion comprises summingmultiple samples in a first half of the signal for the bit to form thefirst sum (sumH1), wherein the summing multiple samples in the secondportion comprises summing multiple samples in a second half of thesignal for the bit to form the second sum (sumH2), wherein the symboltiming error is further determined based on a number of samples in eachof the first sum and second sum (accumlength), wherein the symbol timingerror is determined using the following calculations: when sumH1 isgreater than or equal to sumH2:symbol timing error=sumH1+sumH2−accumlength; and when sumH1 is less thansumH2:symbol timing error=−(sumH1+sumH2−accumlength).
 6. The method of claim1, wherein: modulation is performed in accordance with a near-fieldcommunication type-A standard; estimating the symbol timing errorcomprises comparing a location of a pause in a received signal with anideal location of a pause corresponding to a decoded bit; and adjustingthe symbol timing comprises adding or subtracting the estimated symboltiming error from a sample counter.
 7. The method of claim 1, wherein:modulation is performed in accordance with a near-field communicationtype-F standard.
 8. The method of claim 1, wherein: modulation isperformed in accordance with a near-field communication type-B standardin which data is sent in characters; estimating the symbol timing errorcomprises detecting timing of a beginning of each character; andadjusting the symbol timing comprises incrementing initial symbol timingby a fixed bit duration.
 9. The method of claim 1, wherein: modulationis performed in accordance with a near-field communication type-Bstandard in which data is sent in characters; estimating the symboltiming error comprises detecting timing of a beginning of each characterand comparing a location of a low-to-high or high-to-low transition in areceived signal with an ideal location of a transition; and adjustingthe symbol timing comprises adding or subtracting the estimated symboltiming error from a sample counter.
 10. A receiver forinductively-coupled communications, comprising: a receive antenna forreceiving a signal from an inductively coupled communication device; aslicer that receives output samples from an analog-to-digital converterand generates a bit stream; an acquisition block that acquires packetsand initial symbol timing; a decoder; and a time tracker block thatanalyzes the signal to estimate a symbol timing error based on theinitial symbol timing and the bit stream and adjusts symbol timing tocorrect for the symbol timing error by adding or subtracting theestimated symbol timing error from a sample counter that counts samplesfrom a start of a symbol, wherein the time tracker block provides thesymbol timing to the decoder, wherein the time tracker block analyzesthe signal by: summing multiple samples in a first portion of the signalfor a bit to form a first sum; summing multiple samples in a secondportion of the signal for the bit to form a second sum; determining thesymbol timing error based on at least the first sum and the second sum.11. The receiver of claim 10, wherein the estimating the symbol timingerror comprises the time tracker block comparing a location of a pause,a low-to-high or a high-to-low transition in the received signal with anideal location of a pause or a transition.
 12. The receiver of claim 10,wherein: modulation is performed in accordance with a near-fieldcommunication type-A standard; estimating the symbol timing errorcomprises the time tracker block comparing a location of a pause in areceived signal with an ideal location of a pause corresponding to adecoded bit; and adjusting the symbol timing comprises the time trackerblock adding or subtracting the estimated symbol timing error from asample counter.
 13. The receiver of claim 10, wherein: modulation isperformed in accordance with a near-field communication type-F standard.14. The receiver of claim 10, wherein: modulation is performed inaccordance with a near-field communication type-B standard in which datais sent in characters; estimating the symbol timing error comprises thetime tracker block detecting timing of a beginning of each character;and adjusting the symbol timing comprises the time tracker blockincrementing initial symbol timing by a fixed bit duration.
 15. Thereceiver of claim 10, wherein: modulation is performed in accordancewith a near-field communication type-B standard in which data is sent incharacters; estimating the symbol timing error comprises the timetracker block detecting timing of a beginning of each character andcomparing a location of a low-to-high or high-to-low transition in areceived signal with an ideal location of a transition; and adjustingthe symbol timing comprises the time tracker block adding or subtractingthe estimated symbol timing error from a sample counter.
 16. Acomputer-program product for inductively-coupled communications, thecomputer-program product comprising a non-transitory computer-readablemedium having instructions thereon, the instructions comprising: codefor causing an electronic device to receive a signal from an inductivelycoupled communication device; code for causing the electronic device toanalyze the signal to estimate a symbol timing error, comprising: codefor summing multiple samples in a first half of a portion of the signalfor a bit to form a first sum; code for summing multiple samples in asecond half of the portion of the signal for the bit to form a secondsum; code for determining the symbol timing error based on at least thefirst sum and the second sum; and code for causing the electronic deviceto adjust symbol timing to correct for the symbol timing error by addingor subtracting the estimated symbol timing error from a sample counterthat counts samples from a start of a symbol.
 17. The computer-programproduct of claim 16, wherein: modulation is performed in accordance witha near-field communication type-A standard; the code for causing theelectronic device to estimate the symbol timing error comprises code forcausing the electronic device to compare a location of a pause in areceived signal with an ideal location of a pause corresponding to adecoded bit; and the code for causing the electronic device to adjustthe symbol timing comprises code for causing the electronic device toadd or subtract the estimated symbol timing error from a sample counter.18. The computer-program product of claim 16, wherein: modulation isperformed in accordance with a near-field communication type-F standard.19. The computer-program product of claim 16, wherein: modulation isperformed in accordance with a near-field communication type-B standardin which data is sent in characters; the code for causing the electronicdevice to estimate the symbol timing error comprises code for causingthe electronic device to detect timing of a beginning of each character;and the code for causing the electronic device to adjust the symboltiming comprises code for causing the electronic device to incrementinitial symbol timing by a fixed bit duration.
 20. The computer-programproduct of claim 16, wherein: modulation is performed in accordance witha near-field communication type-B standard in which data is sent incharacters; the code for causing the electronic device to estimate thesymbol timing error comprises code for causing the electronic device todetect timing of a beginning of each character and code for causing theelectronic device to compare a location of a low-to-high or high-to-lowtransition in a received signal with an ideal location of a transition;and the code for causing the electronic device to adjust the symboltiming comprises code for causing the electronic device to add orsubtract the estimated symbol timing error from a sample counter.